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? semiconductor components industries, llc, 2013 august, 2013 ? rev. 0 1 publication order number: PCA9511A/d PCA9511A hot swappable i 2 c-bus and smbus bus buffer the PCA9511A is a hot swappable i 2 c ? bus and smbus buffer that allows i/o card insertion into a live backplane without corrupting the data and clock buses. control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus cont ention on the card. when the connection is made, the PCA9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated. the PCA9511A rise time accelerator circuitry allows the use of weaker dc pull ? up currents while still meeting rise time requirements. the PCA9511A incorporates a digital enable input pin, which enables the device when asserted high and forces the device into a low current mode when asserted low, and an open ? drain ready output pin, which indicates that the backplane and card sides are connected together (high) or not (low). during insertion, the PCA9511A sda and scl lines are precharged to 1 v to minimize the current required to charge the parasitic capacitance of the chip. features ? bidirectional buffer for sda and scl lines increases fan ? out and prevents sda and scl corruption during live board insertion and removal from multipoint backplane systems ? v/ t rise time accelerators on all sda and scl lines ? active high enable input ? active high ready open ? drain output ? high ? impedance sda and scl for v cc = 0 v ? 1 v precharge on all sda and scl lines ? supports clock stretching and multiple master arbitration/synchronization ? v cc operating range: 2.7 v to 5.5 v ? i 2 c and smbus scl clock frequency up to 1 mhz ? alternate features for pca9510a/pca9512a/pca9513a/pca9514a ? available in: micro8, soic ? 8 ? esd performance: 8000 v hbm, 600 v mm, 2000v cdm ? these are pb ? free devices applications ? cpci, vme, advancedtca cards and other multipoint backplane cards that are required to be inserted or removed from an operating system micro8 dm suffix case 846a http://onsemi.com a = assembly location l = wafer lot m = date code y = year w = work week = pb ? free package marking diagrams see detailed ordering and shipping information on page 15 of this data sheet. ordering information 9511 ayw 1 8 (note: microdot may be in either location) 1 8 soic ? 8 case 751 9511 ayww 1 8
PCA9511A http://onsemi.com 2 feature selection feature selection chart feature pca9510a PCA9511A pca9512a pca9513a pca9514a idle detect yes yes yes yes yes high ? impedance sda, scl pins for v cc = 0 v yes yes yes yes yes rise time accelerator circuitry on sdan and scln lines yes yes yes yes rise time accelerator circuitry hardware disable pin for lightly loaded systems yes rise time accelerator threshold 0.8 v versus 0.6 v improves noise margin yes yes ready open ? drain output yes yes yes yes two v cc pins to support 5 v to 3.3 v level translation with improved noise margins yes 1 v precharge on all sda and scl lines in only yes yes 92 a current source on sclin and sdain for picmg applications yes block diagram figure 1. block diagram of PCA9511A
PCA9511A http://onsemi.com 3 pin assignment figure 2. soic8 / micro ? 8 PCA9511A pin descriptions symbol pin description enable 1 chip enable. grounding this input puts the part in a low current (< 1 a) mode. it also disables the rise time accelerators, isolates sdain from sdaout and isolates sclin from sclout. sclout 2 serial clock output to and from the scl bus on the card sclin 3 serial clock input to and from the scl bus on the backplane gnd 4 ground. connect this pin to a ground plane for best results. ready 5 open ? drain output which pulls low when sdain and sclin are disconnected from sdaout and sclout, and goes high when the two sides are connected port. sdain 6 serial data input to and from the sda bus on the backplane sdaout 7 serial data output to and from the sda bus on the card v cc 8 supply voltage functional description please refer to figure 1 ?block diagram of PCA9511A?. start ? up an undervoltage / initialization circuit holds the parts in a disconnected state which presents high ? impedance to all sda and scl pins during power ? up. a low on the enable pin also forces the parts into the low current disconnected state when the i cc is essentially zero. as the power supply is brought up and the enable is high or the part is powered and the enable is taken from low to high, it enters an initialization state where the internal references are stabilized and the precharge circuit is enabled. at the end of the initialization state, the ?stop bit and bus idle? detect circuit is enabled. with the enable pin high long enough to complete the initialization state (t en ) and remaining high when all the sda and scl pins have been high for the bus idle time or when all pins are high and a stop condition is seen on the sdain and sclin pins, sdain is connected to sdaout and sclin is connected to sclout. the 1 v precharge circuitry is activated during the initialization and is deactivated when the connection is made. the precharge circuitry pulls up the sda and scl pins to 1 v through individual 100 k nominal resistors. this precharges the pins to 1 v to minimize the worst case disturbances that result from inserting a card into the backplane where the backplane and the card are at opposite logic levels. connect circuitry once th e connection circuitry is activated, the behavior of sdain and sdaout, as well as sclin and sclout, become identical with each acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. a low forced on either sdain or sdaout will cause the other pin to be driven to a low by the part. the same is also true for the scl pins. noise between 0.7v cc and v cc is generally ignored because a falling edge is only recognized when it falls below 0.7 v cc with a slew rate of at least 1.25 v/ s. when a falling edge is seen on one pin, the other pin in the pair turns on a pull ? down driver that is referenced to a small voltage above the falling pin. the driver will pull the pin down at a slew rate determined by the driver and the load initially, because it does not start until the first falling pin is below 0.7 v cc . the first falling pin may have a fast or slow slew rate, if it is faster than the pull down slew rate, then the initial pull ? down rate will continue. if the first falling pin has a slow slew rate, then the second pin will be pulled down
PCA9511A http://onsemi.com 4 at its initial slew rate only until it is just above the first pin voltage, then they will both continue down at the slew rate of the first. once both sides are low, they will remain low until all the external drivers have stopped driving lows. if both sides are being driven low to the same value, for instance, 10 mv by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving that pin will rise until the internal driver pulls it down to the offset voltage. when the last external driver stops driving a low, that pin will rise up and settle out just above the other pin, as both rise together with a slew rate determined by the internal slew rate control and the rc time constant. as long as the slew rate is at least 1.25 v/ s, when the pin voltage exceeds 0.6 v for the PCA9511A, the rise time accelerator?s circuits are turned on and the pull ? down driver is turned off. maximum number of devices in series each buf fer adds about 0.1 v dynamic level offset at 25 c with the offset larger at higher temperatures. maximum offset (v offset ) is 0.150 v with a 10 k pull ? up resistor. the low level at the signal origination end (master) is dependent upon the load, and the only specification point is that the i 2 c ? bus specification of 3 ma will produce v ol < 0.4 v, although if lightly loaded, the v ol may be ~0.1 v. assuming v ol = 0.1 v and v offset = 0.1 v, the level after four buffers would be 0.5 v, which is only about 0.1 v below the threshold of the rising edge accelerator (about 0.6 v). with great care, a system with four buffers may work, but as the v ol moves up from 0.1 v, noise or bounces on the line will result in firing the rising edge accelerator, thus introducing false clock edges. generally, it is recommended to limit the number of buf fers in series to two, and to keep the load light to minimize the offset. the pca9510a (rise time accelerator is permanently disabled) and the pca9512a (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull ? down off. if the v il is above ~0.6 v and a rising edge is detected, the pull ? down will turn off and will not turn back on until a falling edge is detected. figure 3. system with 3 buffers connected to common node consider a system with three buffers connected to a common node and communication between the master and slave b that are connected at either end of buffer a and buffer b in series as shown in figure 3. consider if the v ol at the input of buffer a is 0.3 v and the v ol of slave b (when acknowledging) is 0.4 v, with the direction changing from master to slave b and then from slave b to master. before the direction change, you would observe v il at the input of buffer a of 0.3 v and its output, the common node, is ~0.4 v. the output of buffer b and buffer c would be ~0.5 v, but slave b is driving 0.4 v, so the voltage at slave b is 0.4 v. the output of buffer c is ~0.5 v. when the master pull ? down turns off, the input of buffer a rises and so does its output, the common node, because it is the only part driving the node. the common node will rise to 0.5 v before buffer b?s output turns on, if the pull ? up is strong, the node may bounce. if the bounce goes above the threshold for the rising edge accelerator ~0.6 v, the accelerators on both buffer a and buffer c will fire contending with the output of buffer b. the node on the input of buffer a will go high as will the input node of buffer c. after the common node voltage is stable for a while, the rising edge accelerators will turn off and the common node will return to ~0.5 v because the buffer b is still on. the voltage at both the master and slave c nodes would then fall to ~0.6 v until slave b turned off. this would not cause a failure on the data line as long as the return to 0.5 v on the common node (~0.6 v at the master and slave c) occurred before the data setup time. if this were the scl line, the parts on buffer a and buffer c would see a false clock rather than a stretched clock, which would cause a system error. propagation delays the delay for a rising edge is determined by the combined pull ? up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. if the pull ? up currents are the same, any dif ference in rise time is directly proportional to the difference in
PCA9511A http://onsemi.com 5 capacitance between the two sides. the t plh may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. the t phl can never be negative because the output does not start to fall until the input is below 0.7 v cc , and the output turn on has a non ? zero delay, and the output has a limited maximum slew rate, and even if the input slew rate is slow enough that the output catches up, it will still lag the falling voltage of the input by the offset voltage. the maximum t phl occurs when the input is driven low with zero delay and the output is still limited by its turn ? on delay and the falling edge slew rate. the output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, v cc and process, as well as the load current and the load capacitance. rise time accelerators during positive bus transitions, a 2 ma current source is switched on to quickly slew the sda and scl lines high once the input level of 0.6 v for the pca951 1a is exceeded. the rising edge rate should be at least 1.25 v/ s to guarantee turn on of the accelerators. the built ? in v / t rise time accelerators on all sda and scl lines require the bus pull ? up voltage and supply voltage (v cc ) to be the same. ready digital output this pin provides a digital flag which is low when either enable is low, or the start ? up sequence described earlier in this section has not been completed. ready goes high when enable is high and start ? up is complete. the pin is driven by an open ? drain pull ? down capable of sinking 3 ma while holding 0.4 v on the pin. connect a resistor of 10 k to v cc to provide the pull ? up. enable low current disable grounding the enable pin disconnects the backplane side from the card side, disables the rise time accelerators, drives ready low, disables the bus precharge circuitry, and puts the part in a low current state. when the pin voltage is driven all the way to v cc , the part waits for data transactions on both the backplane and card sides to be complete before reconnecting the two sides. resistor pull ? up value selection the system pull ? up resistors must be strong enough to provide a positive slew rate of 1.25 v/ s on the sda and scl pins, in order to activate the boost pull ? up currents during rising edges. choose maximum resistor value using the formula given below: r pu 800 10 3 v cc(min) 0.6 c where r pu is the pull ? up resistor value in , v cc(min) is the minimum v cc voltage in volts, and c is the equivalent bus capacitance in picofarads (pf). in addition, regardless of the bus capacitance, always choose r pu 65.7 k for v cc = 5.5 v maximum, r pu 45 k for v cc = 3.6 v maximum. the start ? up circuitry requires logic high voltages on sdaout and sclout to connect the backplane to the card, and these pull ? up values are needed to overcome the precharge voltage. see the curves in figures 4 and 5 for guidance in resistor pull ? up selection.
PCA9511A http://onsemi.com 6 (1) unshaded area indicates recommended pull ? up, for rise time < 300 ns, with PCA9511A. (2) rise time without PCA9511A. (1) unshaded area indicates recommended pull ? up, for rise time < 300 ns, with PCA9511A. (2) rise time without PCA9511A. figure 4. bus requirements for 3.3 v systems figure 5. bus requirements for 5 v systems hot swapping and capacitance buffering application figures 6 through 9 ill ustrate the usage of the PCA9511A in applications that take advantage of both its hot swapping and capacitance buffering features. in all of these applications, note that if the i/o cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements difficult to meet. placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. for a given i/o card, the PCA9511A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pf, the connector, trace, and all additional cards on the backplane.
PCA9511A http://onsemi.com 7 remark : the PCA9511A can be used in any combination depending on the number of rise time accelerators that are needed by the system. normally only one PCA9511A would be required per bus. figure 6. hot swapping multiple i/o cards into a backplane using the PCA9511A in a cpci, vme and advancedtca system
PCA9511A http://onsemi.com 8 figure 7. hot swapping multiple i/o cards into a backplane using the PCA9511A in a pci system figure 8. repeater / bus extender application using the PCA9511A
PCA9511A http://onsemi.com 9 figure 9. system with disparate v cc voltages figure 10. typical application v cc > v cc_low r drop is the line loss of vcc in the backplane.
PCA9511A http://onsemi.com 10 maximum ratings symbol parameter value unit v cc supply voltage ? 0.5 to +7.0 v v n input / output voltage sdain, sclin, sdaout, sclout, ready, enable ? 0.5 to +7.0 v i i input current 20 ma i o output current 50 ma i cc dc supply current 100 ma i gnd dc ground current 100 ma t stg storage temperature range ? 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance soic8 (note 1) micro8 146 205 c/w p d power dissipation in still air at 85 c soic8 micro8 856 609 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in v esd esd withstand voltage human body mode (note 2) machine model (note 3) charged device model (note 4) > 8000 > 600 > 2000 v i latchup latchup performance above v cc and below gnd at 125 c (note 5) 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. measured with minimum pad spacing on an fr4 board, using 10 mm by 1 inch, 2 ounce copper trace no air flow. 2. tested to eia / jesd22 ? a114 ? a. 3. tested to eia / jesd22 ? a115 ? a. 4. tested to jesd22 ? c101 ? a. 5. tested to eia / jesd78. recommended operating conditions symbol parameter min max unit v cc positive dc supply voltage 2.7 5.5 v v n input / output voltage 0 5.5 v t a operating free ? air temperature ? 40 +85 c
PCA9511A http://onsemi.com 11 characteristics v cc = 2.7 v to 5.5 v, unless otherwise specified. symbol parameter conditions t a = ? 40 c to +85 c unit min typ max supplies i cc (note 6) supply current v cc = 5.5 v; v sdain = v sclin = 0 v 3.5 6 ma i cc(sd) shutdown mode supply current v enable = 0 v; all other pins at v cc or gnd 0.1 a start ? up circuitry v pch (note 6) precharge voltage sda, scl floating 0.8 1.1 1.2 v v ih(enable) high ? level input voltage 0.7 x v cc v v il(enable) low ? level input voltage 0.3 x v cc v i i(enable) input current on pin enable v enable = 0 v to v cc 0.1 1 a t en (note 7) enable time 110 s t idle(ready) (note 6) bus idle time to ready active 50 105 200 s t dis(en ? rdy) disable time (enable to ready) 30 ns t stp(ready) (note 8) sdain to ready delay after stop 1.2 s t ready (note 8) sclout/sdaout to ready delay 0.8 s i lz(ready) off ? state leakage current on pin ready v enable = v cc 0.3 a c i(enable) (note 9) input capacitance on pin enable v i = v cc or gnd 1.9 4 pf c o(ready) (note 9) input capacitance on pin enable v i = v cc or gnd 2.5 4 pf v ol(ready) (note 6) low ? level output voltage on pin ready v enable = v cc ; i pu = 3 ma 0.4 v rise time accelerators i trt(pu) (notes 10, 11) transient boosted pull ? up current positive transition on sda, scl; v cc = 2.7 v; slew rate = 1.25 v/ s 1 2 ma input ? output connection v offset (notes 6, 12, 13) offset voltage 10 k to v cc on sda, scl; v cc = 3.3 v 0 110 175 mv t plh low to high propagation delay scl to scl and sda to sda; 10 k to v cc ; c l = 100 pf each side 0 ns t phl high to low propagation delay scl to scl and sda to sda; 10 k to v cc ; c l = 100 pf each side 70 ns i li input leakage current sdan, scln pins; v cc = 5.5 v 1 a c i(scl/sda) (note 9) scl and sda input capacitance 5 7 pf v ol (note 6) low ? level output voltage v i = 0 v; sdan, scln pins; i sink = 3 ma, v cc = 2.7 v 0.4 v 6. this specification applies over the full operating temperature range. 7. the enable time can slow considerably for some parts when temperature is < ? 20 c. 8. delays that can occur after enable and/or idle times have passed. 9. guaranteed by design, not production tested. 10. i trt(pu) varies with temperature and v cc voltage, as shown in the ?typical performance characteristics? section. 11. input pull ? up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage to the positive supply rail. 12. the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltag e as a function of the pull ? up resistor and v cc voltage is shown in the ?typical performance characteristics? section. 13. force v sdain = v sclin = 0.1 v, tie sdaout and sclout through 10 k resistor to v cc and measure the sdaout and sclout output.
PCA9511A http://onsemi.com 12 system characteristics v cc = 2.7 v to 5.5 v, unless otherwise specified. symbol parameter conditions t a = ? 40 c to +85 c unit min max min max f scl (note 14) scl clock frequency 0 400 0 1000 khz t buf (note 14) bus free time between a stop and start condition 1.3 0.5 s t hd;sta (note 14) hold time (repeated) start condition 0.6 0.26 s t su;sta (note 14) setup time for a repeated start condition 0.6 0.26 s t su;sto (note 14) setup time for stop condition 0.6 0.26 s t hd;dat (note 14) data hold time 300 120 ns t su;dat (note 14) data setup time 100 50 ns t low (note 14) low period of scl 1.3 0.5 s t high (note 14) high period of scl 0.6 0.26 s t f (note 14) fall time of sda and scl 20 + 0.1 x c b (note 15) 300 ? 120 ns t r (note 14) rise time of sda and scl 20 + 0.1 x c b (note 15) 300 ? 120 ns 14. guaranteed by design, not production tested. 15. c b = total capacitance of one bus line in pf.
PCA9511A http://onsemi.com 13 typical performance characteristics figure 11. i cc vs. temperature figure 12. i trt(pu) vs. temperature figure 13. input/out t phl vs. temperature figure 14. connection circuitry v o ? v i
PCA9511A http://onsemi.com 14 timing diagrams figure 15. timing for t en , t idle(ready) and t dis figure 16. t stp(ready) that can occur after t en figure 17. t stp(ready) delay that can occur after t en and t idle(ready)
PCA9511A http://onsemi.com 15 test setup figure 18. test circuitry for switching times ordering information device package shipping PCA9511Adr2g in development soic8 (pb ? free) 3000 / tape & reel PCA9511Admr2g micro ? 8 (pb ? free) 4000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
PCA9511A http://onsemi.com 16 package dimensions micro8 case 846a ? 02 issue j s b m 0.08 (0.003) a s t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a-01 obsolete, new standard 846a-02. b e pin 1 id 8 pl 0.038 (0.0015) ? t ? seating plane a a1 c l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max min millimeters ?? ?? 1.10 ?? inches a1 0.05 0.08 0.15 0.002 b 0.25 0.33 0.40 0.010 c 0.13 0.18 0.23 0.005 d 2.90 3.00 3.10 0.114 e 2.90 3.00 3.10 0.114 e 0.65 bsc l 0.40 0.55 0.70 0.016 ?? 0.043 0.003 0.006 0.013 0.016 0.007 0.009 0.118 0.122 0.118 0.122 0.026 bsc 0.021 0.028 nom max 4.75 4.90 5.05 0.187 0.193 0.199 h e h e d d e 8x 0.48 0.65 pitch 5.25 8x 0.80 dimension: millimeters recommended
PCA9511A http://onsemi.com 17 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 PCA9511A/d micro8 is a trademark of international rectifier. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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